CMOS Keyword Spotting VLSI Chip
Baltimore, Maryland, USA
Jan 2026 - May 2026
Low-power CMOS circuit for detecting spoken keywords directly in hardware.
The Problem
Keyword spotting requires converting incoming analog/audio information into a compact hardware architecture capable of identifying predefined frequency patterns.
The Solution at a Glance
Designed a custom CMOS keyword-spotting circuit integrating analog signal processing, frequency comparison, digital storage, and pattern-matching logic into a compact IC layout.
The Approach
Developed an architecture integrating comparators, frequency masks, analog processing blocks, and a 1024-bit shift register.
Designed and simulated individual circuit blocks before system-level integration.
Created transistor-level CMOS layouts for the implemented architecture.
Iteratively optimized layout area while maintaining design-rule and schematic consistency.
Performed DRC and LVS verification on the final design.
My Role
Designer for 1024 Bit Register + Simulation Testing
Simulated, laid out, and verified circuit architecture and designed the 1024 Bit Register in Cadence.
Tools
Cadence
The Results
Built a research-grade digital twin of Guam's isolated electrical grid, modeling generators, inverter-based resources, batteries, solar generation, transmission topology, and line characteristics
